1. Field of the Invention
This invention relates to electrical amplifier designs and methods, and more particularly to amplifiers that use npn bipolar transistors.
2. Description of the Related Art
The schematic diagram of a conventional open loop, unity gain active load amplifier circuit is given in FIG. 1. As explained below, it has low distortion but suffers from slow speed.
The amplifier includes a two-branch input stage, with an npn transistor Q1 in one branch and series connected diodes D1 and D2 in the other branch. The base of transistor Q1 is connected to an input terminal 2 that receives the amplifier's input voltage, while its collector is connected to a positive voltage bus Vcc and its emitter supplies current to an input stage current source I1; the current through the second branch diodes D1 and D2 also flows into I1.
An output stage, consisting of npn output transistor Q2 and an output current source I2 that draws current through the collector-emitter circuit of Q2, provides a voltage signal to an output terminal 4 that is taken from the emitter of Q2. The base of Q2 is biased by the diodes D1 and D2, with another constant current source I3 directing a constant current through the diode branch. The current through diodes D1 and D2 remains nearly constant as the input voltage Vin (and hence the output voltage Vout) vary. As a result, the current through Q1 is also nearly constant; these near constant currents for the input stage result in a highly linear relationship between Vout and Vin, and also produce a low distortion level. However, the transistor base-emitter voltage varies non-linearly with current, leading to distortion for any varying current.
Amplifier stages with active loads such as I3 are discussed in general in Grebene, Bipolar and MOS Analog Integrated Circuit Design, John Wiley & Sons, 1984, pages 232-239. The current source I3 is generally implemented as a pnp transistor. However, to include a pnp transistor in an npn integrated circuit (IC) process, the pnp device is currently implemented as a lateral transistor with high capacitance and is therefore slow, resulting in poor AC performance. This lack of speed limits the resolution of various circuits into which the amplifier can be incorporated. If a faster off-chip pnp transistor is used, the parasitic capacitance and inductance associated with its connection to the chip can significantly reduce its effective speed, in addition to the problem of not being able to include all of the circuit elements on a single chip. Non-monolithic designs are also more expensive and bulky, and less reliable.
The slow speed problems inherent in integrating a pnp current source into a npn amplifier circuit can be avoided by replacing the pnp device with a resistor R1, as illustrated in FIG. 2. This makes high speed operation possible, while simplifying the circuit by eliminating a current source. However, the resistor R1 allows the current through the diode branch to vary as the input voltage changes. As Vin rises, the voltage at the base of Q2 also rises. This reduces the current through R1 and increases the collector current of Q1 (since I1 is constant). This current variation introduces distortion and degrades the amplifier's linearity. The reduction in performance could at least theoretically be mitigated by increasing Vcc from a typical value of 5 volts to a substantially higher value such as 12 volts. This would reduce the effects of voltage variations across R1 due to changes in the input voltage, thereby making the current in the diode branch less sensitive to input voltage variations. But typical power supplies are limited to .+-.5 volts, and in any event increasing Vcc would have the undesired effect of raising the circuit's power consumption.